This application claims the priority of Korean Patent Application No. 2004-40326, filed on Jun. 3, 2004, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field
The disclosure relates to a semiconductor memory device, and more particularly, to a frequency detection circuit to detect the frequency of a clock signal and a latency signal generation circuit having the same.
2. Description of the Related Art
Generally, a synchronous dynamic random access memory (SDRAM) reads data from a memory cell or writes data in to the memory cell in response to an external read command or write command that is received in synchronization with an external clock signal. For example, data is transmitted between the SDRAM and a memory controller through an input/output (I/O) interface in which data is synchronized with a clock signal and transmitted. As transmission frequency increases, it becomes more important to precisely synchronize data with the clock signal. To precisely synchronize data with the clock signal, a conventional SDRAM includes an internal clock signal generator, which generates an internal clock signal and provides the internal clock signal to individual components. The foregoing conventional SDRAM is disclosed in U.S. Pat. No. 6,055,210.
After receiving the read command, the SDRAM outputs data read from the memory cell after a predetermined number of clock cycles. The predetermined number of clock cycles is typically referred to as a latency number. The latency number can be determined according to the operating frequency of the SDRAM. For example, the latency number of an SDRAM having a high operating frequency is set to a higher value than the latency number of an SDRAM having a low operating frequency. Also, the SDRAM includes a latency signal generation circuit, which generates a latency signal. An enabling period of the latency signal is determined according to the predetermined latency number and the length of data to be output (i.e., burst length), and the operation of a data output circuit is controlled by the latency signal. That is, the data output circuit outputs data during the enabling period of the latency signal.
FIG. 1 is a circuit diagram of a data output circuit 10 of a conventional semiconductor memory device.
Referring to FIG. 1, the data output circuit 10 includes a latency signal generation circuit 20, an output controller 30 and an output buffer circuit 40. The output buffer circuit 40 includes an inverter 41, a NAND gate 42, a NOR gate 43, a PMOS transistor 44, and an NMOS transistor 45.
The latency signal generation circuit 20 receives column address strobe (CAS) latency control signals CL1, CL3, and CL4, a read control signal COS, a write control signal PWR, a first internal clock signal DCLK, and a second internal clock signal PCLK, and generates a latency signal LAT. The output controller 30 outputs an output control signal PTRST in response to the latency signal LAT and the first internal clock signal DCLK. The output buffer circuit 40 receives an internal data signal DI and outputs an output data signal DQ in response to the output control signal PTRST.
FIG. 2 is a detailed circuit diagram of the conventional latency signal generation circuit 20 shown in FIG. 1.
Referring to FIG. 2, the latency signal generation circuit 20 includes an input logic circuit 21, an input latch circuit 22, a first switching circuit 23, a second switching circuit 24, a first delay latch circuit 25, a second delay latch circuit 26, and an output logic circuit 27. The first and second switching circuits 23 and 24 are turned on or off in response to the CAS latency control signals CL4 and CL3, respectively. The input latch circuit 22 operates in response to the second internal clock signal PCLK, and the first and second delay latch circuits 25 and 26 operate in response to the first internal clock signal DCLK. That is, the input latch circuit 22 operates only when it receives the second internal clock signal PCLK, and the first and second delay latch circuits 25 and 26 operate only when they receive the first internal clock signal DCLK.
The first internal clock signal DCLK and the second internal clock signal PCLK are generated by a first internal clock signal generator (not shown) and a second internal clock signal generator (not shown), respectively. The first internal clock signal generator is synchronized with an external clock signal EXCLK and sequentially generates the first internal clock signal DCLK while the semiconductor memory device is being enabled. On the other hand, the second internal clock signal generator is synchronized with the external clock signal EXCLK and generates the second internal clock signal PCLK only when the semiconductor memory device externally receives a read command READ. Accordingly, when the semiconductor memory device does not receive the read command READ, the second internal clock signal PCLK is not generated, and the input latch circuit 22 stops operating. At this time, even if the first and second delay latch circuits 25 and 26 receive the first internal clock signal DCLK, since the first and second switching circuits 23 and 24 are turned off, the first and second delay latch circuits 25 and 26 cannot receive any signals and thus, also stop operating. As a result, since the operation of the latency signal generation circuit 20 is stopped while the read command READ is not received, the current used by the latency signal generation circuit 20 may be reduced. The latency signal generation circuit 20, which is embodied so that the input latch circuit 22 operates in response to the second internal clock signal PCLK, operates more preferably when the frequency of the external clock signal EXCLK is reduced. However, as the frequency of the external clock signal EXCLK increases, the likelihood of malfunction of the latency signal generation circuit 20 increases. More specifically, as the frequency of the external clock signal EXCLK increases, the operating speed of the latency signal generation circuit 20 should be increased in proportion to the frequency of the external clock signal EXCLK. However, since the second internal clock signal PCLK is generated after the read command READ is received, the input latch circuit 22 cannot operate at the same time as when the read command READ is received. Thus, the latency signal generation circuit 20 generates a wrong latency signal LAT.
This phenomenon will be described in detail with reference to FIG. 3, which is a timing chart showing input and output signals of the latency signal generation circuit 20 shown in FIG. 2. FIG. 3 exemplarily illustrates a case where the CAS latency control signal CL4 is enabled and the first switching circuit 23 is turned on. The input latch circuit 22 latches an initial input signal LAT0 during a low level period of the second internal clock signal PCLK and outputs the initial input signal LAT0 as a latch signal LAT3 in synchronization with a rising edge of the second internal clock signal PCLK. Similarly, the first delay latch circuit 25 latches the latch signal LAT3 during a low level period of the first internal clock signal DCLK and outputs the latch signal LAT3 as a latch signal LAT4 in synchronization with a rising edge of the first internal clock signal DCLK. Also, the second delay latch circuit 26 latches the latch signal LAT4 during a low level period of the first internal clock signal DCLK and outputs the latch signal LAT4 as a latch signal LATB in synchronization with a rising edge of the first internal clock signal DCLK. However, since the second internal clock signal PCLK is generated after the read command READ is generated, a time margin E from when the first delay latch circuit 25 latches the latch signal LAT3 until the first delay latch circuit 25 outputs the latch signal LAT4 is reduced. As a result, the first delay latch circuit 25 is likely to latch a wrong signal. Referring to FIG. 3, the time margin E required for the latch operation of the first delay latch circuit 25 is even smaller than a time margin D required for the latch operation of the input latch circuit 22 or a time margin F required for the latch operation of the second delay latch circuit 26. This phenomenon becomes more serious with an increase in the frequency of the external clock signal EXCLK.
Meanwhile, to solve these problems, the latency signal generation circuit 20 may be embodied so that all of the input latch circuit 22 and the first and second delay latch circuits 25 and 26 operate in response to the first internal clock signal DCLK. However, in this case, since the input latch circuit 22 sequentially operates during the enabling of the semiconductor memory device irrespective of generation of the read command READ, the current used by the input latch circuit 22 increases. Also, when the latency signal generation circuit 20 operates only in response to the first internal clock signal DCLK when the frequency of the external clock signal EXCLK is low, current is wasted and efficiency is reduced. Therefore, it is required to detect the frequency of the external clock signal EXCLK beforehand so that the latency signal generation circuit can generate a latency signal in response to the result.